Plan 9 can develop a full custom ASIC, design blocks for larger circuits, partition systems information into IC specifications and blocks, develop libraries, and migrate designs into additional processes. Listed below are examples, listed in the following categories, of what Plan 9 has already completed. Please examine our list of accomplishments below.
Plan 9 provides experience in analog, sample data, and mixed-signal integrated circuit design using BiCMOS, CMOS, and bipolar technologies. In addition, Plan 9 offers system partitioning, specification generation, and system modeling services. Plan 9 is capable of taking the IC development from general specifications to integrated circuit specifications and then on through concept, design, and layout. Plan 9 can work independently or as an integral part of your development team. Our experience includes the following:
Low power signal processing circuitry, programmable charge pump, oscillators, references, and a variety of other circuitry for an ultra low power and low leakage chipset.
Active role in the development of the IF portion of an OFDM 802.11a compliant chipset. Activities include developing the gain and frequency partition plan, specifications and AGC algorithm in OFDM 802.11a compliant chipset.
Developed OFDM IF to base-band circuit which includes an LNA, down converter mixer, multistage programmable AGC, active filters, and RSSI detectors.
Provided mathematical system modeling and circuit partitioning support for the development of an ADSL analog front end (AFE). Work includes specifying filter order, gain ranges, noise performance, and other electrical performance goals while making the appropriate trade-off decisions with the customer’s system, DSP and design engineers.
Developed PC board evaluation prototypes of analog portion of ADSL modem. These boards are used to test out software algorithms of the DSP portion of the chipset.
Derived detailed mathematical models of several ADSL line-driver circuits. Models are used to simulate the entire system.
Multi-channel VDSL AFE with 52Mbps down stream capability consisting of a Gm/C and high-speed switched-capacitor filters, PGA’s, serial interface, and data converters. In addition, worked with systems engineers to generate detailed circuit design specifications.
VDSL Transceiver (line interface) featuring a high powered current feedback transmitter, and receiver with programmable hybrid (echo) cancellation circuitry and a 26dB PGA. Wrote specifications for this device as a part of the system partitioning effort listed in the above bullet.
An ADSL AFE with a transmit channel composed of 14-bit D/A, continuous time filter, and transmit power control chip, and a receive channel composed of an LNA, 42dB PGA, and a continuous time anti-alias filter. MTPR measured at 65dB.
Redesigned and transferred data converters used in a wireless communication application from TSMC and Chartered 0.35um mixed signal CMOS process to TSMC 0.15um straight digital process. The circuits included are listed below:
Six-bit pipeline A/D converter running at 22MHz with signal bandwidth of 11MHz.
Current steered six-bit D/A running at 44MHz clock.
Six-bit Flash A/D converter running at 1MHz.
Five layer lateral Metal to Metal capacitor using only metal and no special oxide masks.
Developed a large family of RS485 transceivers in 0.6um BiCMOS process. The process contains 36 V DMOS transistors which are used to meet the extreme requirements of the RS 485 bus pins. Development ranged from the initial feasibility to production ready transceivers included in the customer’s standard part portfolio. The families include 5V, 3V fractional unit load, and Profibus transceivers.
Developed 15 kV HBM ESD cells for the product families above. Presently working on IEC compliant protection devices.
Currently developing dual protocol RS232/485 transceivers with Charge Pump in the above process.
Developed a USB 1.0 transceiver interface circuit in TSMC 0.35um.
Multi-channel SCSI interface drivers.
LVDS standard compliant drivers running 480Mb/s using 2.2V TSMC 0.25um CMOS.
LVDS Clock driver with reduced load requirements runs at 960Mb/s.
LVDS logic family for mixed signal applications in TSMC 0.35um and 0.25um.
Central Office Subscriber Line Interface Circuit (SLIC) packaged in multi-chip module with CODEC, performing BORSCHT functions.
Custom SLIC with multiple feedback loops to achieve longitudinal balance, polarity reversal, and other BORSCHT functions including novel approach to programmable 2-Wire impedance matching and 4-Wire echo cancellation.
VCOM DCP controller used to control panel flicker. Part includes a seven bit DAC, EEPROM, state machine to control memory functions, POR, and up-down counter interface. Integrated in the AMI C5 process (0.5um CMOS).
VCOM DVR controller with EEPROM and I2C slave interface. This product was also developed in the AMI C5 process.
A PLL, Programmable PWM, voltage regulator, oscillator, and I2C slave / multi-master for a Cold Cathode Florescent Light (CCFL) system controller (IBM 0.25um CMOS).
500MHz ATE pin driver offering programmable Voh and Vol, tri-state output, and precision output impedance while maintaining stable transition times and delays.
Large multi-channel signal processing circuit for ECG application containing low power continuous time and sampled data filtering circuits.
Rail to rail input/output operational amplifier family (RRIO op-amps) operating with a VDD as low as 1.8V in a 0.6um CMOS process.
Low noise, high output current, low quiescent current were several of the design goals.
Several Low Drop-Out (LDO) DC voltage regulators designed in 0.6um CMOS process.
Developed 15KV HBM ESD for +12V to -7V pins.
Developed 15KV HBM ESD cells for +25/-25V pins.
Developing IEC capable cells for power supply clamps, RX protection, and TX protection.
Achieved 8KV HBM ESD in the AMI C5 process. Also engineered 2KV protection for 20V pins.
Provided peer review for multi-million dollar ASIC development by attending project milestones, advised customer of development status, and acted as interface between ASIC design vendor and the customer. In addition, Plan 9, Inc. provided layout support in order to expedite the schedule.
Visited ASIC development facility for peer review on the behalf of an equipment manufacturer engaged in an ASIC development. Wrote report outlining ASIC status.
Participated in peer reviews for several military ASIC’s by providing design, layout, tool, and process assistance.