Plan 9 offers experience in analog, sample data, and mixed-signal integrated circuit design using CMOS, HV CMOS, SiGe, and biCMOS technologies. Plan 9 provides IP, full custom ASIC designs, circuit blocks for larger circuits, system partitioning, and migration of designs. Plan 9 is capable of taking the IC development from general specifications to integrated circuit specifications and all the way through concept, design, and layout. Plan 9 can work independently or as an integral part of your development team. Our experience includes the following:
Power Line Communications
- Analog Front-end for power line communications (AFE) both narrow-band (NB) and wide-band.
- Connects to AC power line (110-220V) for High Speed communications
- High speed AFE including line driver and LNA with 70MHz Bandwidth, >50dB MTPR.
- Narrow-band AFE including 3Apk line driver capable of driving a 1ohm load. LNA has high Voltage input range and PGA has -18 to 48dB total gain range. Both have high MTPR.
- Narrow-band AFE is currently offered as IP from Plan 9. (see IP page)
Integrated Circuits for Wearable Devices
- Ultra low power circuitry
- Ultra low off power leakage
- All subthreshold design
- Power savings system implemented
- Circuits include high voltage (50V) charge pump, regulator, oscillators, references, state machines, interface, ESD, etc.
Research and Development of Wearable
- Human compatible, researched anatomy to determine how the circuitry would function with the body and meet FDA safety requirements.
- Very small footprint, flip-chip, also designed flex board
- New to the world application
Ultra-low Power Circuitry
- Low voltage supply operation
- Low power system and circuit design
- 50V High Voltage charge pump, H-bridge
- Regulator, reference, Oscillators, state machines, interfaces
Sensor Research and Development
System design using MEMS sensors
- Complex mathematical solution detected body movement measured by sensors to determine if a movement threshold had been crossed.
- Provided working demonstration of the proposed system design.
System design for Ultrasonic Time-of-Flight
- Performed COMSOL Multiphysics simulations to design miniature ultrasonic transducers geometry, magnitude and frequency response.
- Developed physics-based circuit models for co-simulation of ultrasonic transducer and transistor level circuits.
- Developed system and link budget for distance sensing using ultrasound time of flight. Delivered prototype transducer.
Wearable Device Communications
- Created micro RF antenna design using CST to model antenna and the near body effects
- Performed Radio implementation feasibility for body area network
- Developed Ultrasonic communications concepts for body area network, body to smart device communication and ultrasound ID ( similar to RFID)
- Provided feasibility and analysis of optical communication system
RFID: 13.56MHz Circuitry
- TX and RX analog circuitry, some digital components
Emergency Radio Baseband Transceiver Chip
- 16 Bit Delta Sigma ADC (2nd order)/ DAC (3rd order), Switched capacitor filters and PGA
- Continuous time filters, Digital filters, modulator, and SPI interface
- Low noise, low distortion, 30mm2 Die
Time of Flight precision laser driver
- High speed laser diode driver with up to 1A, 2ns wide current pulses with very low jitter
- 6 Bit current output adjustability
DC/DC Boost power supply
- Nonsynchronous design to provide a quite period for sensitive measuring circuitry.
- RS-485 Compliant +12V, -7V, High REL industrial wire communications
- DDR2 PADS LVDS circuit for high frequency communications
- Development of the IF portion of an OFDM 802.11a compliant chipset. Activities include developing the gain and frequency partition plan, specifications and AGC algorithm in OFDM 802.11a compliant chipset.
- Developed OFDM IF to base-band circuit which includes an LNA, down converter mixer, multistage programmable AGC, active filters, and RSSI detectors.
- 16 Bit Delta Sigma ADC (2nd order)
- 16 Bit Delta Sigma DAC (3rd order)
- Six-bit pipeline A/D converter running at 22MHz with signal bandwidth of 11MHz.
- Current steered six-bit D/A running at 44MHz clock.
- Six-bit Flash A/D converter running at 1MHz.
Interface and Data Communications
- Developed a large family of RS485 transceivers. The families include 5V, 3V fractional unit load, and Profibus transceivers.
- Developed 15 kV HBM ESD cells for the product families above. Presently working on IEC compliant protection devices.
- LVDS interface drivers and receivers Multi-channel SCSI interface drivers.
- LVDS standard compliant drivers running 480Mb/s using 2.2V TSMC 0.25um CMOS.
- LVDS Clock driver with reduced load requirements runs at 960Mb/s.
- LVDS logic family for mixed signal applications in TSMC 0.35um and 0.25um.
- Provided peer review for multi-million dollar ASIC development by attending project milestones, advised customer of development status, and acted as interface between ASIC design vendor and the customer. In addition, Plan 9, Inc. provided layout support in order to expedite the schedule.
- Visited ASIC development facility for peer review on the behalf of an equipment manufacturer engaged in an ASIC development. Wrote report outlining ASIC status.
- Participated in peer reviews for several military ASIC’s by providing design, layout, tool, and process assistance.